One aspect of three-dimensional transistor design is the use of fin structures. These fin structures are raised structures, which serve as the source and drain regions for the three-dimensional transistors. A gate electrode is disposed perpendicularly across the fin structure, separating the source from the drain. The region of the fin structure beneath the gate is referred to as the channel. The application of a bias voltage to the gate causes a conductive path to be formed in the channel, allowing the passage of current from the source region to the drain region. The removal of this bias voltage destroys the conductive path, effectively isolating the drain region from the source region.
Ideally, the conductive path through the channel is the only path through which electrons may move from the source region to the drain region. However, current may leak from the source region to the drain region via a leakage path disposed beneath the fin structure. Specifically, when the fin structure is implanted with the desired dopant, some of this dopant diffuses to a depth beneath that which is intended. For example, the dopant may diffuse to a depth below the shallow trench isolation (STI).
Therefore, it would be beneficial if there were a method of controlling the leakage current in the fin structure of a three-dimensional transistor. More particularly, it would be advantageous to create better isolation of the fin structure from surrounding structures.